This invention relates generally to non-volatile flash memory systems, and, more specifically, to a memory cell structure and process of forming arrays of memory cells that utilize trenches to reduce the overall size of the arrays.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells. Arrays with either a NOR or a NAND architecture are commonly used. One or more integrated circuit chips containing a memory cell array are commonly combined with a controller chip to form a complete memory system. Alternatively, part or all of the controller function may be implemented on the same chip that contains all or part of the memory cell array.
A memory cell array with the NAND architecture utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend over the memory cells in a row direction, across a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,522,580, 6,888,755 and 6,925,007.
There are various programming techniques for causing electrons to travel through the gate dielectric from the semiconductor base structure and onto the charge storage element. The most common programming mechanisms are described in a book edited by Brown and Brewer, “Nonvolatile Semiconductor Memory Technology,” IEEE Press, section 1.2, pages 9-25 (1998), where the charge storage elements are conductive floating gates. One technique, termed “Fowler-Nordheim tunneling” (section 1.2.1), causes electrons to tunnel through the floating gate dielectric under the influence of a high field that is established thereacross by a voltage difference between the control gate and the semiconductor structure channel. Another technique, channel hot electron injection in the drain region, commonly referred to as “hot-electron injection” (section 1.2.3), injects electrons from the cell's channel into a region of the floating gate adjacent the cell's drain. Yet another technique, termed “source side injection” (section 1.2.4), controls the semiconductor structure surface electrical potential along the length of the memory cell channel in a manner to create conditions for electron injection in a region of the channel away from the drain. Source side injection is also described in an article by Kamiya et al., “EPROM Cell with High Gate Injection Efficiency,” IEDM Technical Digest, 1982, pages 741-744, and in U.S. Pat. Nos. 4,622,656 and 5,313,421. In a further programming technique, termed “ballistic injection” high fields are generated within a short channel to accelerate electrons directly onto the charge storage element, as described by Ogura et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, IEDM 1998, pages 987-990.”
Charge is removed from charge storage elements to erase the memory cells. According to one technique, the memory cells are erased to the base semiconductor structure by applying appropriate voltages to the source, drain, semiconductor structure and other gate(s) to cause electrons to tunnel through a portion of a dielectric layer between the charge storage elements and the base structure. A large number of memory cells are grouped together into blocks of a minimum number of cells that are simultaneously erased, in a “flash.” Individual blocks can store a number of pages of data, each page containing one more host sectors' worth of data. The pages are individually programmable and readable. Examples of operating large block memories are given in U.S. Pat. No. 6,968,421.
Currently, electrically conductive floating gates are the most popular form of charge storage elements used in the memory cells. But some flash memories utilize a non-conductive dielectric material that traps electrons. In either case, an individual memory cell includes one or more charge storage elements. Examples of the use of dielectric are described in U.S. Pat. No. 6,925,007 and documents referenced therein. In the case of a dielectric trapped charge memory cell, two or more charge storage elements may be formed as two or more regions of a single continuous layer of dielectric that are spaced apart thereacross. One example of a suitable charge storage dielectric material is a three-layer oxide-nitride-oxide (ONO) composite. Another example is a single layer of silicon rich silicon dioxide material.
As in almost all integrated circuit applications, the pressure to shrink the area required to implement some integrated circuit function also exists with flash EEPROM systems. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon structure, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. Another way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a memory cell threshold voltage range into more than two ranges. The use of four such ranges allows each charge storage element to store two bits of data, eight ranges stores three bits of data per charge storage element, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, as examples.
Some binary memory systems designate the erased state as a data logical “0”, with a programmed state being designated to be a logical “1”. Other binary systems follow an opposite convention, the erased state being designated to be a “1” and the programmed state to be a “0”. In a multi-state system, one having four states per storage element for example, the erased state may be designated as “00” and a maximally programmed state as “11”. Others may reverse these designations.